In /gem5/configs/ruby/MOESI_CMP_directory.py I changed this code:
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc,
start_index_bit = block_size_bits,
is_icache = True)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc,
start_index_bit = block_size_bits,
is_icache = False)
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
send_evictions = (
options.cpu_type ==
"detailed"),
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
cntrl_count += 1
to this:
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc,
start_index_bit = block_size_bits,
is_icache = True)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc,
start_index_bit = block_size_bits,
is_icache = False)
-> l1_cntrl = L1Cache_Controller(version = 0,
cntrl_id = cntrl_count,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
send_evictions = (
options.cpu_type ==
"detailed"),
ruby_system = ruby_system)
-> cpu_seq = RubySequencer(version = 0,
icache = l1i_cache,
dcache = l1d_cache,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.slave
-> exec("system.l1_cntrl%d = l1_cntrl" % 0)
#
# Add controllers and sequencers to the appropriate lists
#
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
cntrl_count += 1
by this way only one L1 cache is created, and
in /gem5/configs/example/ruby_fs.py I changed this code:
for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.createInterruptController()
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
to this:
for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.createInterruptController()
-> cpu.icache_port = system.ruby._cpu_ruby_ports[0].slave
-> cpu.dcache_port = system.ruby._cpu_ruby_ports[0].slave
by this way I connect each cpu's ports to the same sequencer created in
MOESI_CMP_derectory.py and I have used ALPSA ISA.
Pavlos
On Sat, 2012-11-24 at 19:38 -0600, Nilay Vaish wrote:
> On Sun, 25 Nov 2012, Pavlos Maniotis wrote:
>
> > For anyone who would like to share one L1 cache among multiple cpus I
> > have found a possible solution that seems to work:
> >
> > 1) I modified the ruby protocol specific python config file (for example
> > MOESI_CMP_direcory.py in /gem5/configs/ruby) to create just one L1
> > cache, one controller and one sequencer
> >
> > 2) In ruby_fs.py I connected each cpu's cache ports to the one L1 ruby
> > sequencer created in step 1
> >
> > In this way I successfully simulated fft splash2 benchmark in ALPHA fs
> > mode.
> >
>
> I am not convinced that the simulator works correctly without modifying
> the protocol itself. You might want to post your changes to the mailing
> list.
>
> --
> Nilay
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