Hi Pavlos, There is no bus between the CPU core and the L1, just a "port" connection. The PIO bus is only used for PIO, and should not have a great impact on your benchmark unless it is very I/O intensive.
Andreas On 23/11/2012 12:29, "Pavlos Maniotis" <[email protected]> wrote: >Hello everyone, > >I use ruby (MOESI_CMP_directory) and I want to simulate a system >with one CPU (frequency=2GHz) and L1 and L2 caches (frequency=4GHz). >I also want the bus between cpu and cache >to run at 4GHz with width 32 bits. So I have to set the cpu >frequency equal to 4GHz (ruby_fs.py -> CPUClass.clock = '2GHz') >and ruby frequency equal to 2GHz >(Ruby.py -> system.ruby = RubySystem(clock = 4, > stats_filename = options.ruby_stats, > no_mem_vec = options.use_map)). > >I suppose these changes are right, my main concern is: > >Do I have to change system.piobus frequency >to 4GHz and width to 4 bytes (file FSConfig.py, function >makeLinuxAlphaRubySystem)? >Is this the bus between cpu and L1 cache? If it is not >how can I configure the bus between L1 and CPU? > >I am little bit confused about the interconnection system. > >Thanks in advance for any help, >Pavlos > > >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
