On Sun, 25 Nov 2012, Pavlos Maniotis wrote:
In /gem5/configs/ruby/MOESI_CMP_directory.py I changed this code:
by this way I connect each cpu's ports to the same sequencer created in
MOESI_CMP_derectory.py and I have used ALPSA ISA.
I am not convinced that the simulator works correctly without modifying
the protocol itself. You might want to post your changes to the mailing
list.
This violates coherence since more than one processor can assume that they
have write permissions to the same block.
--
Nilay
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