#5506: LLVM AST : needs an LlvmType ctor to represent vectors so that LLVM can
generate SIMD instructions
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Reporter: erikd | Owner: dterei
Type: task | Status: patch
Priority: normal | Component: Compiler (LLVM)
Version: 7.3 | Keywords:
Testcase: | Blockedby:
Os: Unknown/Multiple | Blocking:
Architecture: Unknown/Multiple | Failure: None/Unknown
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Changes (by erikd):
* status: new => patch
Comment:
This code was tested by using the AST definition to generate LLVM IR code
with C calling conventions, running that through first ```llc``` and the
the assembler and then calling into that generated object file from C.
The only caveat is that generated code is really good when the vector
length is a multiple of the vector register length (eg 4, 8, 12 etc for
MMX/SSE) and woefull otherwise (I tested a vector length of 11).
Ran this validate and had 3 completely unrelated failures.
--
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/5506#comment:2>
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