#5506: LLVM AST : needs an LlvmType ctor to represent vectors so that LLVM can
generate SIMD instructions
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Reporter: erikd | Owner: dterei
Type: task | Status: patch
Priority: normal | Component: Compiler (LLVM)
Version: 7.3 | Keywords:
Testcase: | Blockedby:
Os: Unknown/Multiple | Blocking:
Architecture: Unknown/Multiple | Failure: None/Unknown
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Comment(by erikd):
Replying to [comment:3 chak]:
> I am not surprised by this finding. We'll have to break up larger
vector operations into chunks that are a multiple of the vector length and
handle the excess ourselves further up in the compilation pipeline. This
will involve having some knowledge of the target hardware capabilities
further up in the compiler.
I actually think this should be fixed in LLVM. I asked about this in the
LLVM dev mailing list and they say this is a bug. Bug reported here:
http://llvm.org/bugs/show_bug.cgi?id=11023
--
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/5506#comment:4>
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