#5506: LLVM AST : needs an LlvmType ctor to represent vectors so that LLVM can
generate SIMD instructions
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Reporter: erikd | Owner: dterei
Type: task | Status: patch
Priority: normal | Component: Compiler (LLVM)
Version: 7.3 | Keywords:
Testcase: | Blockedby:
Os: Unknown/Multiple | Blocking:
Architecture: Unknown/Multiple | Failure: None/Unknown
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Comment(by chak):
Replying to [comment:2 erikd]:
> The only caveat is that generated code is really good when the vector
length is a multiple of the vector register length (eg 4, 8, 12 etc for
MMX/SSE) and woefull otherwise (I tested a vector length of 11).
I am not surprised by this finding. We'll have to break up larger vector
operations into chunks that are a multiple of the vector length and handle
the excess ourselves further up in the compilation pipeline. This will
involve having some knowledge of the target hardware capabilities further
up in the compiler.
--
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/5506#comment:3>
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