#5506: LLVM AST : needs an LlvmType ctor to represent vectors so that LLVM can
generate SIMD instructions
---------------------------------+------------------------------------------
Reporter: erikd | Owner: dterei
Type: task | Status: patch
Priority: normal | Component: Compiler (LLVM)
Version: 7.3 | Keywords:
Testcase: | Blockedby:
Os: Unknown/Multiple | Blocking:
Architecture: Unknown/Multiple | Failure: None/Unknown
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Comment(by chak):
Replying to [comment:7 erikd]:
> Replying to [comment:6 dterei]:
> > As for the vector 11 size example. Is the poor performance when the
vector isn't length that is multiple of the native vector size?
>
> This one. It needs to be an integer multiple of the native vector size.
But as David wrote, the ticket in the LLVM bug tracker seems to suggest
otherwise:
{{{
It's due to this FIXME in TargetLowering::getVectorTypeBreakdown:
// FIXME: We don't support non-power-of-2-sized vectors for now.
Ideally we
// could break down into LHS/RHS like LegalizeDAG does.
if (!isPowerOf2_32(NumElts)) {
NumVectorRegs = NumElts;
NumElts = 1;
}
}}}
--
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/5506#comment:8>
GHC <http://www.haskell.org/ghc/>
The Glasgow Haskell Compiler
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