From: Ville Syrjälä <[email protected]>

The pcode post notufy needs to happen after the CDCLK has been
changed, not before. Also move the pre_notify call a bit for the
sake of symmetry.

Signed-off-by: Ville Syrjälä <[email protected]>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9718062d8d6c..d60b3369b4d2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2796,9 +2796,6 @@ intel_set_cdclk_pre_plane_update(struct 
intel_atomic_state *state)
                                 &new_cdclk_state->actual))
                return;
 
-       if (display->platform.dg2)
-               intel_cdclk_pcode_pre_notify(state);
-
        if (new_cdclk_state->disable_pipes) {
                cdclk_config = new_cdclk_state->actual;
                pipe = INVALID_PIPE;
@@ -2823,6 +2820,9 @@ intel_set_cdclk_pre_plane_update(struct 
intel_atomic_state *state)
 
        drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
 
+       if (display->platform.dg2)
+               intel_cdclk_pcode_pre_notify(state);
+
        intel_set_cdclk(display, &cdclk_config, pipe,
                        "Pre changing CDCLK to");
 }
@@ -2851,9 +2851,6 @@ intel_set_cdclk_post_plane_update(struct 
intel_atomic_state *state)
                                 &new_cdclk_state->actual))
                return;
 
-       if (display->platform.dg2)
-               intel_cdclk_pcode_post_notify(state);
-
        if (!new_cdclk_state->disable_pipes &&
            new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
                pipe = new_cdclk_state->pipe;
@@ -2864,6 +2861,9 @@ intel_set_cdclk_post_plane_update(struct 
intel_atomic_state *state)
 
        intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
                        "Post changing CDCLK to");
+
+       if (display->platform.dg2)
+               intel_cdclk_pcode_post_notify(state);
 }
 
 /* pixels per CDCLK */
-- 
2.53.0

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