On Wed, 10 Jun 2026, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > We are currently trying to pass the CDCLK in kHz to the pcode > on DG2, while the pcode expects a value in MHz units. Adjust > the units appropriately.
How is it working? :o Fixes: ? > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 9ca56bab281f..9718062d8d6c 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2703,8 +2703,10 @@ static void intel_cdclk_pcode_pre_notify(struct > intel_atomic_state *state) > * if CDCLK is decreasing or not changing, set bits 25:16 to current > CDCLK, > * which basically means we choose the maximum of old and new CDCLK, if > we know both > */ > - if (change_cdclk) > + if (change_cdclk) { > cdclk = max(new_cdclk_state->actual.cdclk, > old_cdclk_state->actual.cdclk); > + cdclk = DIV_ROUND_UP(cdclk, 1000); > + } I'd consider s/cdclk/cdclk_mhz/g here and in intel_pcode_notify() to emphasize it's not kHz. > /* > * According to "Sequence For Pipe Count Change", > @@ -2740,8 +2742,10 @@ static void intel_cdclk_pcode_post_notify(struct > intel_atomic_state *state) > * According to "Sequence After Frequency Change", > * set bits 25:16 to current CDCLK > */ > - if (update_cdclk) > + if (update_cdclk) { > cdclk = new_cdclk_state->actual.cdclk; > + cdclk = DIV_ROUND_UP(cdclk, 1000); > + } Ditto. Reviewed-by: Jani Nikula <[email protected]> > > /* > * According to "Sequence For Pipe Count Change", -- Jani Nikula, Intel
