>Why doesn't it? The wording given is 'The result delay is the number
>of cycles the next sequential instruction would stall if it used the
>result as an input'. I read this as saying that you can ignore the
>result delay, unless the next instruction uses the previous result.
>
>Hence, a ldr r0, [r1], #0 falls into the first category quite definitely,
>since there is writeback of base and there isn't and data extending being
>performed...
I think you've interpreted the table wrong. My understanding is:
The 0 result delay only applies to the updated base register. In other words,
if you do `ldr r0, [r1], #4', the new r1 is available via a bypass for use by
the following instruction.
The destination register always has a result delay of either 1 or 2, depending
on whether it's sign extended or zero extended. If no extension is needed I
guess that counts as zero extension. I'm not sure why there is no bypass for
this case, but I'm no semiconductor expert.
p.
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