Philip Blundell wrote:
> >Is that normal ? There should be no issue delay on ldr, shouldnt it ?
>
> There is no issue delay, but there is a 1-cycle result delay. See the SA110
> instruction timing datasheet -- the destination register of the ldr is not
> available until that instruction leaves the buffer stage.
>
> p.
I was thinking that ldr was "load single - write back of base", not "load
data zero extended"
which for me can only be applied on ldrb and ldrh
What means "write back of base ?"
christophe
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