Re: Instructions timing

[Nicholas Clark]

In the last mail Matthew Wilcox said:

> Yes, this is normal; LDRs have a 1 cycle delay if the register is used
> immediately.  Last I heard; GCC did not reorder instructions to take
> advantage of this.

Q1: Where's the ARMLinux mailing list archive?

IIRC, when I was looking at the ARM gcc backend about a month ago I found no
code to make this optimisation. I think I mentioned that here. Is it likely to
produce > 1% speed increase?

Nick
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