Deborah Wallach writes:
> I think you're misreading the (incredibly cryptic) instruction timing
> table. What mine says is:
>
> Instruction Group Result Delay Issue Cycles
> ------------------------------------- ------------ ------------
> load single - writeback of base 0 1
> load single - load data zero extended 1 1
> load single - load data sign extended 2 1
That's identical to both copies that I have here.
> The first case should only apply to the use of the base register (eg the PC
> in Christophe's example, since his loads are PC-relative). Since the next
> instruction isn't using the PC, but rather the result of the LDR, this
> timing doesn't apply.
Why doesn't it? The wording given is 'The result delay is the number
of cycles the next sequential instruction would stall if it used the
result as an input'. I read this as saying that you can ignore the
result delay, unless the next instruction uses the previous result.
Hence, a ldr r0, [r1], #0 falls into the first category quite definitely,
since there is writeback of base and there isn't and data extending being
performed...
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