From: Russell King - ARM Linux Admin <[EMAIL PROTECTED]>
Date: Wed, 5 May 1999 21:27:56 +0100 (BST)
According to both my SA-1100 and SA-110 documentation, there is no result
delay on either ldr nor the 'eor' instructions when the data resides in
the cache, which in your case it mostly always will be.
I think you're misreading the (incredibly cryptic) instruction timing
table. What mine says is:
Instruction Group Result Delay Issue Cycles
------------------------------------- ------------ ------------
load single - writeback of base 0 1
load single - load data zero extended 1 1
load single - load data sign extended 2 1
The first case should only apply to the use of the base register (eg the PC
in Christophe's example, since his loads are PC-relative). Since the next
instruction isn't using the PC, but rather the result of the LDR, this
timing doesn't apply.
The third case has no relevance for a full word load.
The second case, therefore, must be the timing for a full word load.
-Debby Wallach
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