Re: Instructions timing

[Philip Blundell]

>Yes, this is normal; LDRs have a 1 cycle delay if the register is used
>immediately.  Last I heard; GCC did not reorder instructions to take
>advantage of this.

Actually, I believe it does with -mtune=strongarm110 (or equivalent).  I could 
be wrong, though.

p.


unsubscribe: body of `unsubscribe linux-arm' to [EMAIL PROTECTED]