Re: 440BX-Board (GA-6BXS) and SDRAM initialisation ...

[Eric W. Biederman]

[EMAIL PROTECTED] writes:

> On 12 Feb, Eric W. Biederman wrote:
> > Ronald G Minnich <[EMAIL PROTECTED]> writes:
> > 
> >> On 12 Feb 2001, Eric W. Biederman wrote:
> >> 
> >> > We should enable MTRR's for the RAM being tested in the RAM test.
> >>             ^^^^^^^ disable? don't you want the writes to go to ram, not
> >> be cached?
> > 
> > I want Write-Combining to be enabled.  This is still uncached but enables
> > the write buffers so that you get burts to/from memory.  
> > 
> > Eric
> 
> If write combining doesn't actually cache the data, meaning next time
> you come back and read it it actually reads the ram, then write
> combining should achieve everything needed.  It was bursts that killed
> my almost working system.

That is exactly what write combining does.  It buffers the writes
for a short time but does not put them in the cache.  The writes
aren't perfectly in the order you do them, but as close as to make
no never mind.  I have looked at the effects of this on instrumented
DIMMS so I can say it works as documented.

Eric