On 12 Feb, Richard A. Smith wrote:
> On Mon, 12 Feb 2001 16:53:08 -0500 (EST), [EMAIL PROTECTED] wrote:
>
>>> no never mind. I have looked at the effects of this on instrumented
>>> DIMMS so I can say it works as documented.
>
>>This sounds like the "right thing". RAMTEST with no cache is
>>SSSSLLLOOOOWWWWWWWWW! ...and doesn't test burst.
>>
>
> We were just noticing that today while chaseing down some RAM chip selects that are
> incorrectly wired. We were wondering if our board had some other issues that were
>causing
> that. Good to know that thats the proper behaviour.
>
> But exactly why is it so slow? I mean the ram test routine is only about 20 or so
>assembly
> instructions and reading from flash is still pretty quick... Is there a bunch of
>ISA wait
> states in there or something?
The processor gets real dumb with uncached ISA accesses to
instructions. I'm sure to have some of the details wrong but it is
something like this:
The processor needs and other 32 bit instruction word but only knows
how to fetch 32 BYTES at a time. So each request for a 32 BIT word
gets turned into 64 16 bit ISA accesses. Now, since caching is turned
off competely, it will do an other 64 16 bit ISA accesses for the next
32 bit word even though it has already gotten that info and then some.
Ty
--
Tyson D Sawyer iRobot Corporation
Senior Systems Engineer Real World Interface Div.
[EMAIL PROTECTED] Robots for the Real World
603-532-6900 ext 206 http://www.irobot.com
