Re: 440BX-Board (GA-6BXS) and SDRAM initialisation ...

[tyson]

On 12 Feb, Ronald G Minnich wrote:
> On Mon, 12 Feb 2001 [EMAIL PROTECTED] wrote:
> 
>> This sounds like the "right thing".  RAMTEST with no cache is
>> SSSSLLLOOOOWWWWWWWWW!  ...and doesn't test burst.
> 
> OK, we'll have to put that MTRR WC change in ...
> 
> ron

Enabling caching of the 64K BIOS block may improve performance more
than the write combinging for ram.  Enabling write combining for ram
will mostly test that burst accesses work right.

Ty

-- 
Tyson D Sawyer                             iRobot Corporation
Senior Systems Engineer                    Real World Interface Div.
[EMAIL PROTECTED]                         Robots for the Real World
603-532-6900 ext 206                       http://www.irobot.com