Michael,

I have worked some with Verilog in the past but not much with VHDL. My question 
about the pins was because I recognized that there was a difference in devices 
but I have to admit I hadn’t thought it through well. I will go back to the 
beginning and go through the DE10 tutorial stuff.

Is there a particular reason that you guys are using Quartus version 15.1 
instead of the current 17.1?

Thanks

> On Apr 17, 2018, at 4:30 PM, Michael Brown <mib.holotro...@gmail.com> wrote:
> 
> BTW
> I'm sorry that there is not some nice documentation I can point at describing 
> how to add a new project,
> but here are some notes that have survived:
> https://github.com/machinekit/mksocfpga/tree/master/docs
> 
> 
> On Wednesday, 18 April 2018 01:25:06 UTC+2, Michael Brown wrote:
> 
> Stop ... hold
> On Tuesday, 17 April 2018 05:18:20 UTC+2, mugginsac wrote:
> Michael,
> 
> I have set up a quarts project DE10_Nano_FB_DB25 based on Charles 
> DE0_Nano_DB25 project.
> 
> This is a recipe for disaster.
> 
> ---
> 
> The process is in crude steps:
> 
> You need to start with a DE10_Nano_Soc Board design (ie: the 
> DE10_Nano_FB_Cramps)
> 
> Then the systemverilog .sv topfile  can be replaced with the vhdl .v one from 
> the DE0_Nano_DB25.
> 
> The HDMI framebuffer core is in the Qsys design (in the DE10_Nano_FB_Cramps 
> project), also the lcd clock is placed into the qsys partition.
> 
>  
> I copied the HDMI stuff from your DE10_Nano_FB_Cramps.qsf into 
> DE0_Nano_DB25.qsf to create DE10_Nano_FB_DB25.qsf. There were pin conflicts 
> between the HDMI stuff and the GPIO stuff. So I copied the GPIO stuff from 
> your DE10_Nano_FB_Cramps.qsf as well, but then I got to wondering if that was 
> the right thing to do? Should I have preserved the GPIO pins and changed the 
> HDMI pins to resolve the conflicts?
> 
> 
> Do not edit any pins in the .qsf file these pins are set up for the physical 
> boards and the DE0 nano is very different from the DE10 Nano, so you will 
> only get no-go or smoke...!
> 
> You have to have some basic knowledge about fpga's verilog/vhdl and working 
> with Quartus and qsys for this attempt to succeed, I would not recommend you 
> to continue anything like you are describing ....  
>  
> ---
>  
> Thanks,
> Alan
> 
>> On Apr 16, 2018, at 7:00 PM, Michael Brown <mib.hol...@gmail.com <>> wrote:
>> 
>> Short answer ... Yes
>> 
>> more verbose:
>> Each board needs its own Quartus project folder.
>> 
>> There are 2 options:
>> 
>> 1.
>> To create that bitfile a new quartus project targeting the DE10 Nano Board 
>> with DB25 adaptor,
>> needs to be added here:
>> https://github.com/machinekit/mksocfpga/tree/master/HW/QuartusProjects 
>> <https://github.com/machinekit/mksocfpga/tree/master/HW/QuartusProjects>
>> 
>> With a name like:
>> DE10_Nano_FB_DB25
>> Based on the existing _DB25 Quartus project by Charles
>> 2.
>> As a last resort
>> I can add a 7I76_7I76_7I76_7I76 pin file to the existing DE10_Nano_FB_Cramps 
>> quartus project
>> and create it with a DE10_Nano_FB name and then add something to get the 
>> built in pin mux to configure for the DB25
>> Also needed would be to add the SSerial core.
>> (This will take some time as I'm caught up in updating and debugging my 
>> synthesizer project)
>> 
>> 
>> On Monday, 16 April 2018 20:26:39 UTC+2, mugginsac wrote:
>> Michael,
>> 
>> I followed your instructions down to:
>> 
>>     setenv bitimage 
>> /lib/firmware/socfpga/DE10_Nano_FB_Cramps.3x24_cap_spi.rbf
>>     setenv fdtfile socfpga_cyclone5_de10_nano_fb.dtb
>> 
>> It looks to me like I need something like: 
>> 
>>     setenv bitimage /lib/firmware/socfpga/DE10_Nano_FB_DB25.rbf
>>     setenv fdtfile socfpga_cyclone5_de10_nano_fb.dtb
>> 
>> It looks like the socfpga_cyclone5_de10_nano_fb.dtb may already exist but 
>> that I need to create the DE10_Nano_FB_DB25.rbf.
>> 
>> Is that right?
>> 
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