The FET current is governed not by the output power, but by the inductance and its time constant. The output voltage is immaterial. Once the magnetic energy is stored in the inductor and the current cuts off, that energy WILL be dumped, by hook or by crook, even if it takes a million volts to do it. If you don't have an output capacitor it will rise until something breaks down, which is usually the FET. So it's meaningless to say it needs a duty cycle of X to achieve Y voltage, since it can achieve any Y with any X in a single cycle. With the capacitor in circuit, it will charge it higher by Q/C volts every cycle (where Q = It, the charge generated by the collapsing magnetic field). The calculation you need to apply is how much input power at 24V is needed to maintain the capacitor output voltage at the output current you desire. If it's 200v at 35mA, 7000mW, then that's the power you have to put in (plus losses) at 24V - say 350mA. That's 350mW dissipation at the optimistic typical Rds(on) for 100mA. But 350mA is an average, delivered in pulses of much higher current, and until the capacitor is charged and achieves regulation those pulses will be longer and heavier. The FET will be drawing over an amp in pulses, will have Rds(on) more in the region of 10 ohms and will rapidly heat up, and as it heats up its Rds(on) increases, so it gets hotter, and then it unsolders itself. Believe me, I've seen it happen and still have the holes burned in my fingertips to remind me. You should be looking for an FET with an Rds(on) in the 100 milliohm range at 1 amp. You can experiment and find out for yourself but I strongly recommend the big fat IRL640 - it's threshold is in the 2V range so it should work. There's another reason for this, which is the inductive time constant, L/R. As the on resistance increases the time constant gets smaller, so you need higher inductance to keep it from saturating during the on period.
Controlling the on time is the *only* thing that affects the output voltage. Less on time means less magnetic energy stored in the inductor, so less charge dumped into the capacitor each cycle. But you must always have *some* off time, for that energy to be dumped, as if you don't limit it the PWM can run up to the point where the inductor doesn't have time to discharge fully and still retains some flux. Then next cycle it ramps to a higher flux density, and higher every time, until it saturates and your FET goes up in smoke. My rule of thumb is 20% of the cycle time. You can have less, but the longer the on time, the higher the FET current. I set the PWM pin to an input because that can be done in a single instruction, whereas to drive it low you first have to disable the PWM, and then later it has to be enabled again, which is an unnecessary complication. I just let the PWM continue to run with its output disabled and let the resistor hold the FET off. If you can run the PWM at 200kHz, good luck. With AVRs at a modest clock rate that doesn't allow enough counts for regulation, but with a gigahertz ARM I guess that's not a problem. However, the gate capacitance of the FET has to be driven, and that too has a time constant. The turn on time is unimportant but the turn off time is of the highest importance, since during the interval from where the gate starts to pinch until it shuts off completely, all that stored magnetic energy is being used to heat up the FET, not being dumped into the output. There is always some turn-off loss, every cycle. When the cycle time is 25us you only pay this fare 40k times a second. At 5us you'll pay five times as much. It takes a lot of skill to reduce that loss and it really only became practical to run converters above 100kHz when the switches could be integrated. 200kHz is a worthy aim but a very long drive, across water with deep bunkers on the other bank. On Wednesday, June 10, 2015 at 12:45:41 PM UTC-7, Brian wrote: > > Thank you very much, Pete, for the insights! It will be great to have > someone that's done this before as a resource. I have a few questions. > > First, I did think about driving the FET from 3.3V, so I selected it > carefully. I am using the Vishay TN2404K, and assuming a Vgs of 3.3V, it > looks like Rds(on) is about 2.3 ohms: > > > <https://lh3.googleusercontent.com/-C8b3V6gWFgY/VXhR1u8tLeI/AAAAAAAAVM4/xpHLMYM7F0s/s1600/TN2404K_rdson.png> > > > Assuming 35mA max current draw (ballparking 4 IN-18 tubes as worst case), > the voltage drop across the FET would be about 81mV, and the power > dissipation about 3mW. The datasheet says the FET is capable of 360mW of > dissipation (at room temp), so I felt pretty good about using them. Is > there something I am missing there? > > (As a cheaper alternative I may use the BSS131, which I am already using > to drive the nixie channels. Making the same assumptions, Rds(on) is about > 10.3 ohms, which a voltage drop of 361 mV, and power dissipation of about > 13mW, still well below the limit.) > > Second, I was planning on running the PWM at 200kHz because it allows the > boost to run in continuous mode with a much smaller load. This way I can > test with a single nixie (around 1.5mA). I have worked through the boost > calculations and the PWM register values in a spreadsheet here > <https://docs.google.com/spreadsheets/d/1AlgrgIQSByZBakUH5zwjJ94VcO_23aLYUsACbMPxswc/edit?usp=sharing>. > > Please take a look if you are curious. I may be off base with my desired > values. > > One concern I had based on your feedback is the ratio of the A to B > register. This ratio sets the duty cycle of the PWM output, right? To > boost 24V to 200V, I need to duty cycle of 88%, which exceeds your > recommendation of 80% max. Can you talk a little bit about why this is > important? I know the inductor needs some time to discharge, but isn't > controlling that on/off time the only way to set the output voltage? > > I also had a question about driving the FET gate. Why set the pin to an > input and rely on the pulldown rather than driving the pin low? > > I really like the soft start idea and the guidance about using the ADC > interrupt routine. Plus I appreciate your advice on ramping the voltage up > slowly, I will make sure I take care when testing (and especially > debugging). Good to know about the HV5530 at 5V too! > > -Brian > > On Wednesday, June 10, 2015 at 5:34:19 AM UTC-4, petehand wrote: >> >> I've used the main CPU as the switching regulator in just about all my HV >> projects, and I can tell you exactly how to go about it. A word of warning, >> though - the STM chip is 3.3V VCC. That is exceedingly marginal for turning >> on even a logic level FET of the rating you need. You should probably >> choose a different processor. Anyway, to the technique. >> >> Choose a timer for PWM. It needs two compare registers, one for setting >> the maximum count (A) and one for toggling an output (B). Most CPUs have >> this. Set it up for a free running frequency of at least 30kHz - that is, >> it runs from 0 to max count and resets in 30us. 40kHz is better (25us). It >> doesn't need many bits - 8 bits is fine for this job. Example, if you have >> an 8 bit counter clocked at 8MHz, the modulus (maximum count, 'A' compare >> register) would be 200 for 40kHz. Set this value in the A register and a >> low value, like 1, in the B register. This gives you a soft start. >> >> The pin toggled by the B comparator should be settable as input or >> output. Connect this pin to the FET gate with a 2.2k pulldown resistor. >> When the pin is set as input, this should pull down close to ground to keep >> the FET off. After reset, start off with this pin as input. >> >> Choose an ADC channel and input, and connect through a resistor divider >> to the HV output. Calculate what the ADC reading will be at the desired >> voltage - this will depend on the reference voltage, the resistor values, >> etc. Set the ADC going in free run, with an interrupt on conversion >> complete. >> >> In your ADC interrupt routine, compare the ADC reading to the setpoint >> you calculated. If it is below, increment the counter 'B' compare register >> by 1, up to about 80% of the top value you set in the 'A' compare register. >> Don't go past that point! The FET needs some off time to discharge the >> inductor. Then set the PWM pin as an output. If the ADC reading is above >> the setpoint, decrement the 'B' compare by 1 and set the PWM pin as input, >> to turn off the FET. If it is equal, do nothing. When starting out from >> nothing you may need to limit the B register to less than 80% of A, to >> limit the current. I start mine out with a 25% limit and change that to 80% >> when the voltage comes up above 75%. At low voltage there's no load so it >> comes up quickly even with a low duty cycle. >> >> For 20-30kHz, you need about a 220 to 270 microhenry inductor with a >> saturation current of 1A or more. The IRF640 is a suitable driver. You'll >> find there's a limited choice of high voltage FETs with a logic level gate. >> A technique I've been using for some time is to use a center tapped >> inductor with the FET attached at the center tap. That way it only >> experiences half the HV pulse. >> >> The only problem I have with this system is when I'm debugging and stop >> at a break point. Because the PWM is completely asynchronous there's a good >> chance the processor halts with the FET turned on, and things quickly get >> quite warm. I find it expedient to put a jumper in the FET gate that I can >> remove to shut down the HV. Most of the time when I'm debugging I don't >> need the tubes lit anyway. For the finished clock no doubt you'll have a >> watchdog timer, and the first thing that will do when it trips is turn off >> the PWM port. >> >> If you had a 5V processor you could use the HV5530 with a VCC of 5V and >> no level shifting. It works perfectly well at 5V for nixie currents, but >> not at full speed - the clock timing is about 4 times longer. I've tried it >> at 3.3V though and it's no go. >> >> >> On Tuesday, June 9, 2015 at 5:54:56 PM UTC-7, Brian wrote: >>> >>> I do have a scope, via work. I know a little about switching converter >>> design, but I've never had to design one at this level. Getting the >>> converter right is the main reason I am doing this small board before >>> jumping fully into the project. Hopefully I can lean on you guys a little >>> until I get it right! >>> >>> -Brian >> >> -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. 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