On 5/27/06, josephhenryblack <[EMAIL PROTECTED]> wrote:
two questions for now..
1. For the modules, what code will you accept - verilog or/and vhdl? ( I
can do basic vhdl, but willing to learn.)
Especially in this case, we're doing only one module, and I've already
started designing the interface in Verilog. I will be learning VHDL
this summer, but I don't know it yet. Also, I'm not sure if we can
mix languages in the synthesizers.
2. What software and editing program do you recommend. Looking at some
free ones..
For the SPI controller, it's not performance critical, so there's no
need to emphasize synthesis. Let's focus on simulation and functional
correctness. Anything chip specific (like a block ram or DDR I/O
buffer) I can provide simulation modules for.
The tools you need are Icarus Verilog for simulation and a wave viewer
like GTKWave (although I want to find something better). Those are
typically available as packages for your distro. Gentoo has ebuilds
for them, and Ubuntu has them in the universe.
Here's how to use icarus to 'compile' and 'execute' a design:
iverilog spi.v spi_test.v
./a.out
And here's how to view the wave forms:
gtkwave test.vcd
There's code you have to put into the test module to make it output waves:
initial begin
$dumpfile( "test.vcd" );
$dumpvars;
#5000; // duration of simulation
$finish;
end
Editors... I use nedit, but it doesn't matter. The coding style I
prefer is four spaces to a 'tab stop', but without any actual hard
tabs.
So, a random piece of my code will look like this:
initial begin
clock_1x = 1;
forever begin
#10;
clock_1x = !clock_1x;
end
end
BTW, don't think I'm ignoring what you have to say about synthesizers.
Getting some people started on them is good. It's just that what you
said covered the issues. :)
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