Timothy Miller wrote: > On 5/27/06, josephhenryblack <[EMAIL PROTECTED]> wrote: > >> two questions for now.. >> 1. For the modules, what code will you accept - verilog or/and vhdl? ( I >> can do basic vhdl, but willing to learn.) > > > Especially in this case, we're doing only one module, and I've already > started designing the interface in Verilog. I will be learning VHDL > this summer, but I don't know it yet. Also, I'm not sure if we can > mix languages in the synthesizers. >
Some synthetizer accept both language in the same design. But it must be by doing call to the others block. For example you have the spi prom interface in vhdl you instanciate it in a verilog design, the contrary could also be true. One simulator who can do that is "modelsim". For the synthesis there is "Precision Synthesis" who can also do it. Normally fpga company their synthesis program have a interface module for precision synthesis. Only problem with these software is the cost. For the rest they work like a charm and if I remember correctly they work in windows, linux, hp-ux and solaris. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
