On Thu, 2006-10-05 at 11:36 -0400, Timothy Miller wrote: > On 10/3/06, tsuraan <[EMAIL PROTECTED]> wrote: > > > > > > > In hardware a groups of blocking assignments get registered all in > > > parallel, independent of one another, even if some earlier lhs is > > > found in the rhs of a later assignment. > > > > > > With blocking assignments, the order matters, and so dependencies will > > > cascade. A lhs that appears in a later rhs will result in a longer > > > chain of combinatorial logic. > > Just for reference's sake, the first paragraph is actually referring to > > non-blocking assignment, right? > > > > Yes, you are right! I'm sorry about that. That's kindof a critical > mistake for me to make there...
ok, I think I understand now. It is really strange thinking that everything runs in parallel, but I think it makes sense. I added my module into the template you wrote, but it was complaining about FDDRRSE, as in this: module ddrff1(Q, C0, C1, D0, D1, OE); input C0, C1, D0, D1, OE; output Q; wire R; FDDRRSE ff0 (.Q(R), .C0(C0), .C1(C1), .CE(1'b1), .D0(D0), .D1(D1), .R(1'b0), .S(1'b0)); assign Q = OE ? R : 1'bz; endmodule I am just using iverilog test_head0.v -o testhead0 to compile it. Is there some special library or parameter I need to compile it? nick _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
