On 10/6/06, Nicholas <[EMAIL PROTECTED]> wrote:
ok, I think I understand now. It is really strange thinking that everything runs in parallel, but I think it makes sense.
Just think of every continuous or nonblocking assignment as a separate thread in a program.
I added my module into the template you wrote, but it was complaining about FDDRRSE, as in this: module ddrff1(Q, C0, C1, D0, D1, OE); input C0, C1, D0, D1, OE; output Q; wire R; FDDRRSE ff0 (.Q(R), .C0(C0), .C1(C1), .CE(1'b1), .D0(D0), .D1(D1), .R(1'b0), .S(1'b0)); assign Q = OE ? R : 1'bz; endmodule I am just using iverilog test_head0.v -o testhead0 to compile it. Is there some special library or parameter I need to compile it?
In another thread, I posted this module. Here it is again: module FDDRRSE(Q, C0, C1, CE, D0, D1, R, S); output Q; reg Q; input C0, C1, CE, D0, D1, R, S; always @(posedge C0) Q <= D0; always @(posedge C1) Q <= D1; endmodule Add this to your test module that wraps the video module. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
