On Sun, August 19, 2007 1:30 pm, Timothy Normand Miller said: > On 8/19/07, Farhan Mohamed Ali <[EMAIL PROTECTED]> wrote: > >> My university teaches some classes on P&R algorithms, according to a >> friend of mine who took it the algos are not very complex. Don't know >> if that is really true. But i think this is for ASICs, not FPGAs, maybe >> it's harder for FPGAs because there are more restrictions. > > Some of the research I've been doing lately has to do with > performance-driven randomized algorithms. (That's not a technical term, > just how I think about it.) So, we have these hard problems, in part > because they're NP-hard but also because it's difficult to decide the > best way to map the abstract logic to real gates--everything is > influenced by the context of how all the other logic gates are mapped to > real hardware. Using a genetic algorithm or simulated annealing or > whatever, we can have the algorithm just TRY stuff, and we rate attempts > based on the performance of the final result. I don't want to bore you > with stuff you probably already know. The point is that the restrictions > needn't be a major burden on us. Instead of deciding where to place > something based on some prediction of how it'll perform, different > placements are judged based on how they actually perform. > > The thing about simulated annealing, as compared to GAs, is that SA only > has one population member. I suspect that it could be overwhelming to > use a GA due to the memory requirements to represent one population > member, and to make a GA work well, you need very many population members > and a lot of processing time to manage each. It would be nice to have an > algorithm that works reasonably well on your own PC. On the other hand, > we could also develop something that takes advantage of clusters; imagine > if Google or someone were to get interested and offered the ability to > submit synthesis jobs to their cluster. > >From what little i have seen, current P&R tools are still way behind what a reasonably experienced person can do in terms of area and performance, especially for blocks like ALUs where the critical paths are generally known in advance and placement is usually quite logical (for a human). But of course they are MUCH faster than hand layouts, and are perhaps a little better for a bunch of random logic like complex FSMs and such. So this is certainly a nice research area. Transistors/chip are increasing at a much faster rate than the number of chip designers, so good P&R tools would be great. I think it doesn't really matter if you need a cluster to run it, current tools are also very time consuming to run. The quality of the layout is more important IMHO.
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