On 8/19/07, Dieter <[EMAIL PROTECTED]> wrote:
> > On the other hand, we could also develop something that takes
> > advantage of clusters; imagine if Google or someone were to get
> > interested and offered the ability to submit synthesis jobs to their
> > cluster.
>
> Would it be practical to do floss-chip-design-at-home similar to
> folding-at-home, seti-at-home, ... ?
>
> If so, it would then be easy to run the final design on multiple
> OSes and multiple CPU arches to catch FDIV type bugs.  Testing the
> app itself enough to trust it and have the ma$k built would be a lot
> of work.  Any wild guesses on how much code it would be?
>
> Or is testing the FPGA version sufficient?

I don't know what it would take.  But I think we could look into it.
I might suggest an approach.  How about we begin by developing some
code that, given a fully-routed design, could perform an analysis of
timing and other characteristics?  This would be the part of a GA, for
instance, that calculates the "objective function."  (If we're going
to take the cluster approach, let's use a genetic algorithm, why not.
But we can also consider other types of evolutionary algorithms.)

For school, I've developed a pluggable GA framework for Ruby.  For the
moment, what's implemented is an experimental multicriterial
algorithm.  But shortly, I have to implement SPEA2 so I can have a
point of comparison for a paper I'm writing.  We could adapt this
framework a bit and implement the FPGA evaluation block.  (Ruby is
slow for this kind of performance critical thing like P&R, but we can
move important blocks into C extensions, leaving the high-level stuff
in Ruby.  Or we can use the prototype as a reference and rewrite the
whole thing in C/C++ later.)

Also, we could consider using the PISA framework.
http://www.tik.ee.ethz.ch/sop/pisa/

-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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