On 11/7/07, Michael Meeuwisse <[EMAIL PROTECTED]> wrote: > > We have a full-blown PCI controller that you can look at in the SVN > > repository. That talks to verious bits of logic in the XP10, > > implementing things like PCI config space, the bridge logic, HQ (not > > yet, but eventually), and that sort of thing. The bridge is a local > > bus between the two FPGAs, using our own custom protocol (or whatever > > you want) just for accessing memory and engine address spaces. > > Ok, but this is the controller for PCI on the XP10, not the FPGA. I > was suggesting our own custom bridge-protocol would be very similar > to PCI, so we could re-use bits and pieces of this module. Also > instantly gives us things like full signal waveforms for read/write > operations etc - just look at the PCI docs.
The XP10 _IS_ an FPGA. And it's not a tiny one either. It's just much smaller than the Spartan. But you have some good points about how we might shape our protocol for debugging. Note that PCI is way overly complex for what we need for the bridge. The bridge logic is much simpler. > > Exactly, although it's, what you might call our 'bridge protocol', but > > I think you knew that. > > Wait, what? What do you mean with 'graphics memory'? Is it our big > chunk of main memory, on the other side of the FPGA? I can hardly > imagine having something like; > Step 1, write to initial buffer: CPLD -> FPGA -> DDR > Step 2, read initial buffer: DDR -> FPGA -> CPLD > Step 3, crunch data with HQ. > Step 4, write to frame buffer: CPLD -> FPGA -> DDR > > That would put quite some traffic on the bridge. Can I make the > suggestion that (if above is correct) we don't do that 'font > translation' with the HQ, but in realtime in the video controller? I did say this was going to be slow. It just doesn't _matter_ that it's slow. Remember, this VGA thing is bandaid and a minimal one at that. Also, this is a reason why we pipeline requests. Make a bunch of read requests, then wait for the data. This makes up for a lot of the latency. Oh, and in VGA mode, we may saturate the bridge. So what. This is not a performance-critical situation. The more performance-critical situation is in dealing with PCI transactions that we have to intercept, so HQ needs to be connected directly to the PCI controller. > > Yes. This is the video controller (also in SVN already). > > I missed that, is that vid_ctl? I think so. There's more than one. Look for the one that has Patrick McNamara's name in the copyright. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
