On Nov 5, 2007 7:04 PM, Michael Meeuwisse <[EMAIL PROTECTED]> wrote: > Let me start off by saying that I still think you're all doing a > fantastic job, and that my comments where (and are) meant to be > constructive, not offensive. If it sounded otherwise, I apologise in > advance.[1]
I didn't think you did anything that would warrant an apology... I just took advantage of the opportunity to vent. :) > I probably went out of line there, but in my defence it felt like you > were saying that the only way out of this loop would be some > community members jumping in and closing the gap (which I personally > feel is there), while I think that it might be wiser that you would > temporarily stop pushing for the PCB, help us catch up with > documenting, and then continue. See what Terry said. For most people, we're a non-project until we produce something that people can touch. OGD1, even with weak documentation, is critical for the project. > That's exactly why I started firing off a dozen questions about the > bridge. Good! Questions are good. Answers are good. And having some others help put them all on the wiki is even better. :) > > I believe this would fit nicely on the VGARoadmap page, I'll add a > written out version to it this weekend hopefully (unless somebody > beats me to it). Thank you for that! > > This is exactly the kind of stuff I wanted to hear. I had no idea it > was DDR. Well, it doesn't HAVE to be. They're just pins on chips, after all. You can assign them whatever meanings you want. However, the way we've been using it is DDR. This has to do with a combination of things, including signal integrity on the clock line and the clocks that are actually available to us. Given that we had a 100MHz clock but wanted to do 200MHz, we just made all the buffers to DDR. > I just want to recap in my own words to make sure I > understood everything. So we'll end up with a more-or-less PCI > controller on the FPGA, which has C/BE[3:0] and AD[0:31] lines. We have a full-blown PCI controller that you can look at in the SVN repository. That talks to verious bits of logic in the XP10, implementing things like PCI config space, the bridge logic, HQ (not yet, but eventually), and that sort of thing. The bridge is a local bus between the two FPGAs, using our own custom protocol (or whatever you want) just for accessing memory and engine address spaces. > I also figure we end up with IRDY/TRDY/FRAME and an interrupt line. > DEVSEL, IDSEL and STOP can probably be left out, as well as PERR and > SERR, although some sort of recovery must be available. We don't bother with SERR, but all the rest are implemented. > I assume this 'scratchpad' memory is in the XP10 and only a few > (hundred, tops) bytes big. VGA text mode requires more than one text buffer. I think it's like 8, and then there's the font. That's enough that we need to put it into graphics memory. > The HQ translates it, and then does a 'pci > write' to a framebuffer on the FPGA. Exactly, although it's, what you might call our 'bridge protocol', but I think you knew that. > Finally, there's a separate > (which isn't part of HQ or the VGA controller) module on the FPGA > constantly reading that framebuffer and passing it on to the DAC. Yes. This is the video controller (also in SVN already). > > Some pieces are out there, some aren't. Can you make sense of VGA > > from what I've described above? If not, ask more questions! > > Yep, pretty much. I assume that the specific VGA registers are > intercepted by the HQ and never moved in any way to the FPGA, > correct? Right. The I/O space "legacy" VGA registers are caught by HQ and just stored in scratch memory (that's a 512x32 memory inside the XP10). > I also assume that the address of the framebuffer on the > FPGA, as well as the settings for the video rasterscan controller > (mode etc) are done in registers, but we haven't defined yet which > registers (might as well start at 0x01? How big is this register > space going to be?) are going to be what option. I forget how large we defined the engine space to be. 256K? Doesn't really matter, since we can change it at will. The video controller has a local register space that is defined. We just haven't settled where it'll start in the engine address space. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
