Dieter wrote:
With
sufficient hardware, you can do my sample problem at the rate of one
output per clock. HOWEVER, it will require 9 hardware multipliers and 6
adders vs only 3 of each for the vector processor. To do 4 vector * 4x4
Transform matrix (which is required for RGBA pixels), it will require 16
hardware multipliers and 12 adders.
Are we really going to have that kind of hardware available?
Is that really a huge amount of hardware, given how many transistors/gates
a modern ASIC has?
No, it isn't a huge amount of hardware compared to ASIC chips which
exist or compared to a processor chip. However, we are using an FPGA
and the question becomes: will it fit in the FPGA which we have chosen?
Specifically, the FPGA has a fixed number of multiplier arrays and
when we use all of them, that is it.
The goal here is the OGC board.
The plan is to design an ASIC to put on the board. (Unless we find
a suitable DSP or whatever that will do the job.)
Granted we want to keep the size of the ASIC reasonable, for both cost
and power/heat reasons. We want the ASIC to be significantly smaller
than the monsters that ATI and Nvidia are cranking out. My question is,
would the 16 multipliers and 12 adders be reasonable, or would that
push the ASIC into the expensive and power hungry territory?
I was suggesting 16 MACs (4 more adders). I don't see that as being
excessive (either cost or power wise) compared to the monster
microprocessors that are currently being produced.
Note that in addition to this that we will also need YUV <-> RGB
hardware which is common on many SOCs.
The FPGA is a tool to design the ASIC. If the entire ASIC design
can't fit into the FPGA at once, perhaps it can be tested in pieces.
Perhaps we could use more than one OGD1 together?
Lets see. The XCS3000 has 96 18x18 multipliers so 16 32 bit float
multipliers would seem reasonable (4 for each), leaving some for the
color space conversion.
--
JRT
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