Dieter wrote:
With
sufficient hardware, you can do my sample problem at the rate of one
output per clock. HOWEVER, it will require 9 hardware multipliers and 6
adders vs only 3 of each for the vector processor. To do 4 vector * 4x4
Transform matrix (which is required for RGBA pixels), it will require 16
hardware multipliers and 12 adders.
Are we really going to have that kind of hardware available?
Is that really a huge amount of hardware, given how many transistors/gates
a modern ASIC has?
No, it isn't a huge amount of hardware compared to ASIC chips which
exist or compared to a processor chip. However, we are using an FPGA
and the question becomes: will it fit in the FPGA which we have chosen?
Specifically, the FPGA has a fixed number of multiplier arrays and
when we use all of them, that is it.
--
JRT
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