Le 2012-11-12 17:27, Nicolas Boulay a écrit :
This look like "split transaction" in AMBA world. But it could be
nice
to have every read split to hide the latency of the memory access.
This is the normal way of doing in a network with "packet" transfer.
You could do this on the cpu level, with a register to wrote the
adress you want to read and a register for the data to be written. If
you have 20 of such dual register, you could handle 20 memory stream
at the same time. Only read on the data register will block, if the
data is not ready. You could use the adresse register bank to do
complexe prefetch if you want.
hey, you almost described how the YASEP accesses memory :-)
but there are only 5 register pairs.
yg
_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)
