Hi,

I stumbled upon this thread via twitter.

This is a brilliant idea. I don't know why we haven't thought about
combining the open graphics project in the ASIC. Let's discuss this
some more and see if we could come up with a practical solution. I
have read about the open graphics project in the past, but I'm a bit
out of the loop, so here's a few newbie questions:

1. Do you need dedicated RAM, and in that case, which size and bandwidth?
2. How many gates is the current design?
3. Is it in a state that could be targeting an ASIC right now, or do
you need more functionality and verification?
4. We are not sure yet if we will be targeting an ASIC with gigabit
transceivers. Would that be a requirement?

Looking forward to discuss this more

Best Regards,
Olof
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