On Thu, Nov 8, 2012 at 2:50 AM, Olof Kindgren <[email protected]> wrote:
> Hi, > > I stumbled upon this thread via twitter. > > This is a brilliant idea. I don't know why we haven't thought about > combining the open graphics project in the ASIC. Let's discuss this > some more and see if we could come up with a practical solution. I > have read about the open graphics project in the past, but I'm a bit > out of the loop, so here's a few newbie questions: > > 1. Do you need dedicated RAM, and in that case, which size and bandwidth? > Actually, I'd prefer to have unified RAM and moreover, I'd prefer to have virtual addressing for the GPU. > 2. How many gates is the current design? > Zero. Right now, we're working on the simulator, and we have a fairly complete architectural definition. I'm sure this is not what you were hoping to hear. (Vaporware, etc.) But in the past incarnation of the OGP, RTL was never a bottleneck. The PCB for OGD1 was what held everything up. I've got an NSF proposal due in mid December. Once that's in, I plan to start coding the "reference" design for the GPU. That will evolve, but what you guys need is quite scaled down compared to our ultimate target. You could get by with a handful of shaders. > 3. Is it in a state that could be targeting an ASIC right now, or do > you need more functionality and verification? > It's C code right now. I hope to have Verilog some time very early 2013 if plans work out well. Unless someone else steps up who's good at coding Verilog, I expect to do that almost entirely myself, which is fine, because I'm pretty fast at that. I can get help from graduate and undergraduate students to perform functional verification at least at the RTL level. Then I can get some people in ECE at various schools to help with the synthesis and gate-level verification and optimization. > 4. We are not sure yet if we will be targeting an ASIC with gigabit > transceivers. Would that be a requirement? > I think that even if you decide that we're not what you're after, I think your project would be an excellent design target. How would you feel about a design that was appropriate for embedded devices? Look at the PowerVR designs used in mobile devices; only like 4 shader engines. The only gigabit transceivers I can think of would be for if you were to incorporate DVI encoding directly into your ASIC. SO! If you haven't decided to write us off already, let us know your requirements, because this is an opportune time for us to tune things to your needs. > Looking forward to discuss this more > > Best Regards, > Olof > _______________________________________________ > Open-graphics mailing list > [email protected] > http://lists.duskglow.com/mailman/listinfo/open-graphics > List service provided by Duskglow Consulting, LLC (www.duskglow.com) > -- Timothy Normand Miller, PhD Assistant Professor of Computer Science, Binghamton University http://www.cs.binghamton.edu/~millerti/<http://www.cse.ohio-state.edu/~millerti> Open Graphics Project
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