Don't forget the software stack to create before than any open graphic card became usefull : linux (windows ?) drivers, shader compiler, 3D stack,... This could represent more work than the RTL design.
If your software stack is very clean you could have a market, even for a low end card. 2012/11/4 Timothy Normand Miller <[email protected]>: > I've done a lot of FPGA work. While it's true that there's way more > flexibility with standard cell, making it work on FPGA is not necessarily a > huge burden, and making an ASIC is _always_ more expensive. I'm not > suggesting that everyone should make it run on FPGA. Just those of us who > are trying to test the design before taking the risk of making an ASIC. > (Even so, there will still be enough changes between FPGA and ASIC that the > FPGA testing doesn't have full coverage, but it's a great way to find a lot > of bugs in the core design.) > > Anyhow, this is a ways off. It's lunacy to design a chip before you have a > full functional simulator. > > > On Sat, Nov 3, 2012 at 6:55 PM, Troy Benjegerdes <[email protected]> wrote: >> >> On Sat, Nov 03, 2012 at 01:44:18PM -0400, Timothy Normand Miller wrote: >> > Let's not make this so overwhelmingly large that no one sees the end. >> > That's one of the problems we had with the OGP originally. >> > >> > Let's break this down into some steps: >> > 1. Design simulator for GPU >> > 2. Design RTL for GPU >> > 3. Get it to work in RTL-level simulation >> >> Let's stop at 3, to keep this simple. If we start talking about >> targeting FPGAs, we start jumping through hoops, and engineering >> creative work-arounds, only to find ourselves with a $1500 fpga >> board. >> >> We don't need something that has gee-whiz features, we just need >> something with a PCI-E 1x port, an hdmi output (maybe with an >> encoder chip to avoid obnoxious licensing questions). There are >> things like http://www.mosis.com/what-is-mosis that significantly >> reduce the cost of ASIC design. >> >> What's the rush? Let's go with a relatively ancient process, and >> try to produce RTL for a GPU that works with an opencores OpenRisc >> CPU core, and clocks at 200mhz. >> >> At this point, I'm actually inclined to think that going straight >> to ASIC is *easier*, because we can simulate the proposed ASIC >> from first-principles, instead of depending on some black-box >> vendor fpga tools that just break in strange ways. > > > > > -- > Timothy Normand Miller, PhD > Assistant Professor of Computer Science, Binghamton University > http://www.cs.binghamton.edu/~millerti/ > Open Graphics Project > > > _______________________________________________ > Open-graphics mailing list > [email protected] > http://lists.duskglow.com/mailman/listinfo/open-graphics > List service provided by Duskglow Consulting, LLC (www.duskglow.com) _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
