On 13.03.2018 21:14, Christopher Head wrote:
On March 13, 2018 12:21:47 PM PDT, Tomas Vanek via OpenOCD-devel 
<openocd-devel@lists.sourceforge.net> wrote:
Obviously faster DAP WAIT handling on USB HS.
The question remains: why are you getting DAP WAITs with algo, is the
different adapter FT2232H vs FT2232C (should not be different except
faster turnaround but...) or is it a difference between STM32F722 and
F745 ?
This is indeed an interesting question. I don’t have an F722 to test with. I 
also don’t have a 2232C.
Damn I neglected that I had to decrease adapter_khz.

I tried some experiments. First I tried mucking about with CM7_AHBSCR to 
increase the priority of AHBS accesses to the DTCM over CPU accesses; no 
change. Then I tried eliminating the AHBS altogether by putting the work area 
at 0x20010000 (system SRAM); also no change. Finally I tried changing dap 
memaccess; this did help. When I changed from the default of 8 up to 44 (43 was 
not enough), I got no more WAITs and 150 kiB/s.

Did you use 'adapter_khz 8000'  for the last test?
I'm afraid that 8 MHz is too much (WAITs during reset-init). I copied the value from STM32F4 config to be consistent. ST-Link limits the clock to 4 MHz so who knows if 8 MHz was really tested. Anyway F4 does not suffer from WAIT problem. Try to comment out "adapter_khz 8000" in -event reset-init definition. 2000 kHz should work with default memaccess 8
(if not please find the memaccess limit).

So, what now? Is that setting something that belongs in the F7 target file?

Especially if the value depends on internal flash timing in such broad range as 16usec typ 100 usec max ...

Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
OpenOCD-devel mailing list

Reply via email to