On Dienstag, 13. März 2018 01:32:24 CET Tomas Vanek via OpenOCD-devel wrote:
> On 12.03.2018 21:53, Christopher Head wrote:
> > On March 10, 2018 11:25:15 PM PST, Tomas Vanek via OpenOCD-devel <openocd-
de...@lists.sourceforge.net> wrote:
> I got much worse results with DAP WAIT on a slow old Intel Atom single
> core industrial PC:
> speed as slow as 3.618 KiB/s (without wait 48.723 KiB/s).

Just a general remark on WAIT with cheap USB shift register drivers: Even with 
a proper implementation of WAIT handling so that it is not treated as an error 
any more, the performance will be abysmal. Especially for large block writes, 
once you hit a WAIT condition, all following writes will be discarded, but 
since we do only check the result at the end of a block to save time on the 
fast path, a lot of discarded writes have to be replayed slowly and 
synchronously and that will take a lot of time.

You will always have the best performance if you carefully tweak your write 
speed so that you reach optimum performance without ever producing a WAIT 
response. HLA adapters or CMSIS-DAP with SWD have a clear advantage here, 
because they can do a proper synchronous WAIT at the JTAG or SWD link layer 
and not up in the ADI protocol.


Mit freundlichen Grüßen/Best regards,

Matthias Welwarsky
Project Engineer

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