From: Roberto <[EMAIL PROTECTED]> Date: Mon, 21 Jun 2004 22:44:10 +0200
I know that 9600's (and 9500's) PCI slots are managed by two Bandit chips: one manages 3 stlots (A1, B1, C1) and one the other three (D2, E2, F2). I read that controller cards (like FireWire, SCSI or IDE cards) have to be inserted in the topmost slots (A1, B1, C1) for functioning properly. I read also that particularly demanding cards, like video or audio cards, should preferably be put in those topmost slots too.
BUT...
I read also that the best performing slots are A1 and D2, and that controller cards etc. should be inserted there.
So, which is the truth?
Cards should not care whether they are in the upper (Bandit 1; A1, B1, C1) slots or the lower slots (Bandit 2). In fact, the performance should be slightly better in the lower slots depending on your use.
It is true (sometimes) that the top slot on each bandit may be best performing. This is becasue of a software artifact either in the ROM or the OS by Apple and has to do with support for 32 byte cache line transfers. If your card doesn't need these transfers, it won't care whether it's in the top slot or not. This issue is documented in Apple's Tech Note TN_1008.pdf, "Understanding PCI Bus Performance":
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As an example, if two cards (card x and card y) have addresses mapped into segment 8, one at 0x80800000 and another at 0x80801000, the first call to SetProcessorCacheMode from the driver of card x to make a cacheable address space in segment 8 will work. A second call, say from the driver of
card y, to modify the cache setting in segment 8 will not work nor will it report an error. This scenario will most likely result in a lower than expected performance for card y, because card y address space is actually cache inhibited which disables PCI transactions of 32-byte cache lines. If the two cards are mapped into different segments, such as 8 and A, then they both can modify the cache settings within
their perspective segments. This limitation will be relaxed in the future.
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To better understand the Bandit architecture it helps to visualize the overall machine architecture. Computers are built on hierarchies of busses. A bus is a collection of signals (wires) which are delivered to all the components on the bus. All the members of a bus share these signals. There are various schemes so that the members of the bus will know when to talk and when to listen on the bus and these schemes are called bus arbitration.
A chip which sits on two busses and translates between them is called a bridge. It bridges communications between the two busses.
The PM9500's top level bus is the CPU/memory bus. On this bus reside the CPU(s), the memory controllers, and the Bandit chips. The Bandit chips are on the CPU bus on one side and on the PCI bus on the other side. So the Bandit chips are CPU/PCI bridges.
Each Bandit chip has it's own PCI bus. So the 9500/9600 has two independent PCI busses each supported by its own PCI bridge. The PowerSurge architecture (the family to which the x500, x600 machines belong) can support up to four Bandits on the CPU bus, in theory.
Arbitration on the Power Surge PCI bus is provided by a separate chip from the Bandit. The Bandit chip can support up to 16 PCI slots on the PCI bus. The Arbitration chip has support for six PCI slots. Electrical limitations keep the total down to five slots or ten permanent devices. Of course, Apple didn't get close to these limitations in their implementation.
Bandit 1 actually supports four PCI devices. There are the three PCI slots, but there is also the Grand Central (343S1125) chip, which is a PCI device. Grand Central collects the I/O signals for the PM motherboard and sends them to the PCI bus. So all of the ethernet, sound in/out, floppy, SCSI, etc. signals go through Grand Central and end up on the PCI bus 1 supported by Bandit 1.
Bandit 2 just supports the bottom three PCI slots.
So you can see where there is actually more traffic through Bandit 1 than through Bandit 2 and that is why performance may be better on Bandit 2 than on Bandit 1.
There is one other factor though which may play a part. Bus arbitration on the CPU/memory bus, which decides when the CPU, memory controller or each bandit gets to use the bus, is mysterious (not documented) and a litttle screwy. The arbitration scheme should treat each Bandit just the same, in which case Bandit 2 would still be a better place to be performance-wise. But it is possible that Bandit 1 gets some type of preference or just comes first in the rotation.
The problem with G4 processors in the six slot machines, has at its root a bug in the CPU/memory bus arbitration scheme. The arbitration for the CPU/memory bus is handled by Hammerhead (343S1190).
So, in theory, the Bandit 2 slots should yield better performance. The top slot on each PCI bus may yield better performance because of the cach-line issue, but Apple claimed this would be addressed in a later OS release. And it is possible that Bandit 1 will actually be better than Bandit 2 depending on how the CPU bus arbitration actually plays out, but I don't think that is a factor in practice.
Jeff Walther
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