Matt (and everybody!), There's really no need to eyeball gerbers to check connectivity. A much quicker and better (semi-)automated gerber check can be done as follows:-
1. Generate gerbers as normal. 2. Generate an IPC-D-356 netlist from the PCB layout tool. This is generated from the PCB file itself (*not* from the gerbers) and, in rough terms, contains a textual description of the gerbers. IPC netlist can be generated in DXP SP2 from CAM generation, Insert TestPoint Report (you might have to check a few boxes first time round.) Do not generate the IPC netlist from within Camtastic! 3. Open a new blank Camtastic document. 4. Import the copper layer gerbers and drill files into Camtastic. No need to bother with paste, resist, silkscreen etc. 5. Within Camtastic, generate a netlist from the gerber files. 6. Within Camtastic, compare the netlist with the IPC netlist file (the one you exported from the PCB in step 2). Steps 4-6 are covered in the help files under something like 'Importing/checking Gerbers'. I'm not actually at the machine with DXP installed, so I can't be any more detailed, but it's only been a couple of weeks since the last time I did this. The PCB vs gerber netlist check will likely give you warnings about unconnected pads (fixing holes and so on), but should otherwise match. If not, the gerbers do match the PCB file. Simple as that. As an extra safety check, I always send the IPC netlist with the gerbers to the fab house and ask them to compare their gerber-generated netlist with the supplied IPC netlist - before they start etching! At worst case you'll lose a day of their pre-processing time. But at least you won't waste days/weeks making and assembling a batch of useless boards. I can't emphasise this point enough: the IPC netlist is generated from the PCB design and *not* from the gerbers. As long as you remember that, its purpose becomes obvious. Sorry this won't help you this time round, but it's saved my bacon several times over the years. I got burned long ago with stitching vias which connected Power and Ground layers together, and looked around for the solution. Well, I asked the fab guys... I can't really believe more people don't supply their fab house with IPC netlist along with gerbers. My fab house tells me I'm their only customer who does. I guess everybody else ends up with more respins than I do! Sorry for my late reply. Cheers, Steve Matt Polak wrote: > > Hey Gang, > > We've come across a *major* show-stopper problem on some > boards we just got back from our board house. For whatever reason, > there are a few spots where DXP decided that our vias should just not > randomly connect to the power planes their nets are assigned to. Most > of the board is fine, but we've already found one major cluster that's > problematic. Take a look at this... > > http://www.raven-systems.com/temp/missing_connections.gif > > As you can clearly see, when viewing the power plane > connections in the layout editor, the interconnects show fine. When > viewing the verbatim generated Gerbers, however (RIGHT IN DXP!) there > are missing plane connections! The entire top set of 7 vias are not > connected to ANY planes, whilst the bottom row are connected just fine > where appropriate. I looked at the properties of all of the top-row > vias, and they're just fine - nothing out of the ordinary. > Surprisingly most of the other vias on the board (including the bottom > row) connect just fine!! > > Has anyone seen this, or know of a way to have DXP scan for > it, or fix it? We just lost a lot of time and money on this > spin-and-assemble due to this export problem, and I have a feeling > we'll likely be finding more of these little via issues as we continue > to bring the board up. And worse yet, we have to do another Gerber > generation - am I going to have to hand-check several thousand vias on > the Gerber outputs to ensure this doesn't happen again? > > Honestly, this is bringing me to an absolute last straw in > continuing to use Protel if we can't even be guaranteed consistent > WYSIWYG output. Someone PLEASE tell me we did something wrong? I'm > starting to lose patience with Altium's little "features" in the > software. > > Frustrated as hell, > -- Matt ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
