break the keep out line in the area of the pads and/or make a rule for a tiny clearance to that pad
have done both of those
but beware that most fabs want at least 20 mils from edge of hole to edge of bd
HTH
Dennis Saputelli
_______________________________________________________________________ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st Street Fax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com
Nukien wrote:
Hi again -
This is with P99SE-SP6. Take a look at the image (if it comes though that is). I have a power connector that needs to mount very close to the edge of the pcb. So much so that one of the plastic guide pins on it will actually be right on the edge, and two of the pads will be touching the keepout layer line.
In the pic, the colors are :
Beige - Faceplate position Dark purple - PCB outline Bright green - Keepout layer highlighted by clearance constraint violation
The only violation being generated is a clearance constraint between pad J1 and the track on the keepout layer. It's actually touching the keepout layer track ...
I can't seem to get a clearance constraint rule that will allow this just for the one J1 component. The keepout layer isn't a choice in the rules, and I don't want to set the clearance to 0, or the polygon fills will touch the pad I think.
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