I would normally break the keepout either side of each pad, just enough so that the DRC errors disappear.
I don't think it's possible any other way... TC -----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Nukien Sent: Tuesday, 5 April 2005 8:09 AM To: Protel EDA Discussion List Subject: [PEDA] How to set clearance constraint for pads close to keepoutlayer Hi again - This is with P99SE-SP6. Take a look at the image (if it comes though that is). I have a power connector that needs to mount very close to the edge of the pcb. So much so that one of the plastic guide pins on it will actually be right on the edge, and two of the pads will be touching the keepout layer line. In the pic, the colors are : Beige - Faceplate position Dark purple - PCB outline Bright green - Keepout layer highlighted by clearance constraint violation The only violation being generated is a clearance constraint between pad J1 and the track on the keepout layer. It's actually touching the keepout layer track ... I can't seem to get a clearance constraint rule that will allow this just for the one J1 component. The keepout layer isn't a choice in the rules, and I don't want to set the clearance to 0, or the polygon fills will touch the pad I think. -- Dean Carpenter deano at areyes com 94TT :) ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
