Bruce,
        the issue of thermal stress cracking was not directly related to the
thermal reliefs of vias. The thermal stress cracking was the reason for
filling the vias with solder to supply a more reliable via under thermal
extremes. The thermal relief just allowed easier soldering of the vias to
meet the desired end result.

Sincerely,

Brad Velander
Lead PCB Design
Norsat International Inc.
#100 - 4401 Still Creek Dr.,
Burnaby, B.C., Canada.
V5C6G9.
voice: (604) 292-9089 (direct line)
fax:    (604) 292-9010
email: [EMAIL PROTECTED]
www: www.norsat.com


-----Original Message-----
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Bruce Walter
Sent: Wednesday, February 21, 2001 1:34 PM
To: Multiple recipients of list proteledausers
Subject: [PROTEL EDA USERS]: Plane Stitching


<SNIP>

Now, I don't solder to these stitches, so I have them as direct connect.
Did I see something suggesting this could have thermal stress cracking
problems on FR4?  If so, how does the thermal relief lessen this effect? (no
solder)

<SNIP>



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