but what about electro plated full body gold over nickel, isn't that ok?

I have heard of (actually read about) BGAs having cracked joints due to
shock when boards are immersion gold plated.

Dennis Saputelli

Mark E Witherite wrote:
> 
> Hi,
>          The Gold causes enbrittlement.  NASA now requires that the gold
> plated surfaces that become part of the finished solder connection shall be
> removed by 2 or more successive tinning operations.  (reference section
> 7.2.5c  NASA-STD-8739.3)
> 
> Got to run
> Mark
> 
> At 04:55 PM 4/17/01 -0400, you wrote:
> >Andrew.
> >Are you involved with developing flight boards?   From time to time I will
> >do a flight design for NASA/GSFC in Md.  GSFC has a spec S-312, that
> >prohibits anything except  tin/lead hasl finish for flight boards. Gold /
> >white tin, etc are strictly prohibited .   When we spec a board out tin/
> >lead is the only choice.   I am not sure about the chemical /molecular
> >interaction between gold and tin but, I know they don't like gold plated
> >boards for flight.   There is apparently  migration from the gold to the
> >tin, and somehow this translates into reduced reliability ( can anyone
> >elaborate on this?)   I'm not even sure if this a specific problem to the
> >environment in space or just an interaction between gold and solder.   For
> >that reason, we don't use gold or white tin plating.
> >
> >Interestingly, many component leads will be gold plated on flight approved
> >hardware.  Go figure that one out
> >
> >
> >Mike Reagan
> >EDSI
> >
> >
> >
> >----- Original Message -----
> >From: Andrew J Jenkins <[EMAIL PROTECTED]>
> >To: Protel EDA Forum <[EMAIL PROTECTED]>
> >Sent: Tuesday, April 17, 2001 3:29 PM
> >Subject: Re: [PEDA] Gold Emersion
> >
> >
> > > On 01:17 PM 4/17/01 -0400, [EMAIL PROTECTED] said:
> > > >Can anyone direct me to some research papers published about the
> >advantages
> > > >and disadvantages of using Gold emersion on mulitlayer pcbs. I have only
> > > >heard information from pcb vendors but would like to see something
> > > >published. Any documentation that includes manufacturing results would be
> > > >great.
> > >
> > >
> > > Have you checked PCB and SMT magazines? I believe that both have published
> > > articles on plating in the past, and they might offer a bit more objective
> > > treatment than what might be expected from the PCB houses. EDN might also
> > > have something to offer, as they have treated PCB mfg-ing in the past
> > > (though I can't remember how recently...)
> > >
> > > Also, try
> > > regards,
> > >
> > >
> > >
> > >
> > > 2.2   S E C O N D   D R O P   T O W E R
> > > Andrew J Jenkins        Electrical Engineer
> > > National Center for Microgravity Research
> > > NASA-Glenn Research Center MS 45-1
> > > 21000 Brookpark Rd, Cleveland OH 44135
> > > (216) 433-5001 fax:433-3793
> > > [EMAIL PROTECTED]
> > >
> > >
> >
> 
> Mark Witherite
> Sr Research Technologist
> Astronomy & Astrophysics
> Penn State University
> 2565 Park Center Blvd
> Suite 200
> State College, PA.  16801
> email [EMAIL PROTECTED]
> telephone 814 865 9839
> fax           814 865 9100
> IPC PWB  Certified

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