Well Ted it is supposed to be possible through the Short Circuit Constraint
in the Other Design Rules Tab. Last anybody ever tried it, it still didn't
work but that was a little while ago. That might have been before SP6, I
don't remember.

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


> -----Original Message-----
> From: Ted Tontis [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, July 12, 2001 1:29 PM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] "Trace" jumpers generate DRC violations
> 
> 
> You would hope that with as many people who have had this 
> problem or needed
> a work around, Protel would realize that they should add 
> something to the
> design rules. Possibly a design rule that lets you have a 
> zero clearance
> between a net. Or the ability to open the track attributes 
> and check a box
> that lets you short them, without a DRC error.
> 
> Ted
> 

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