At 08:56 AM 9/5/01 +1000, Ian Wilson wrote:
Abd ul-Rahman, I agree with your comment that it can be depressing when you 
are told not to do something rather than how...but...

I agree completely with:


>We take the view that any socketed items are actually part of a higher 
>level assembly than the PWA (printed wiring assembly).  The PWA includes 
>just the items that are run through the soldering process.  Any extra 
>things like ROMs or socketed protection components appear on the next 
>higher level assy parts list.  We use the Sch as the primary source for 
>the PWA parts list but this has extra bits added, like the PCB.  We 
>usually do not try to include all PWA bits in the Sch, but I am aware that 
>some people do.  Doing this would certainly be easier if we had Sch symbol 
>and PCB footprint attributes to prevent them being involved in 
>synchronization and to be ignored during netlist import - as has been 
>discussed recently.

I want to underscore the point that in nearly every case the PCB is itself 
a component belonging to a higher-level assembly. And the unstuffed board 
belongs on the BOM for the assembly. That a Protel schematic will generate 
a BOM is a tool properly used in two ways: (1) For an informal environment 
where BOMs are not necessarily complete, or (2) to generate data which can 
be used to prepare a formal and complete BOM. We have seen posts on this 
list as to how to transfer the Protel Schematic BOM data to other programs. 
Trying to prepare a formal and complete BOM in Schematic would be like 
trying to use Protel PCB for architectural drawings. You can do it, but not 
if one wants to make a living at it!

[...]
As for the original question, what about:
>1) Create socket footprint with all the pins/pads, but a minimum of overlay
>2) Create IC footprint which is just overlay/silkscreen (no pins/pads)
>3) Position together on PCB carefully
>4) Create a union to ensure they move together

Yes. This is a very good way to do it. It also applies to other parts. For 
example, one may make a heat sink footprint and unite it with a power 
transistor, or a light pipe footprint and unite it with an LED.

>5) Pressure Protel to allow correct handling of negative component 
>clearances to allow for overlapping components, I have an yone else want 
>to add a voice....

Yes, the component clearance rule needs work. This should be added to the 
"bug" database. I consider it a bug because most designers work with some 
footprints that would normally have zero clearance on the outline when 
placed (and because the outline has a line width, this becomes overlap). 
Some outlines are designed to be butted up against each other when packed 
on-grid. (i.e., the outline includes tolerances). So the existing component 
clearance DRC is often unusable.

http://groups.yahoo.com/group/protel-users/database

(one must be a member of [EMAIL PROTECTED] to access the 
database, and a log-in is required and at least a session cookie accepted, 
I think.) Please do not post directly to the bug database but submit bugs 
or suggestions to Mr. Wilson:

[EMAIL PROTECTED]

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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