Mike,

I too would like th see the ability to control the "removal" of the inner
pad propr to the "gerber file generation" stage, but for a different reason.

Polygon fills around a pad on a signal layer, are based on the pad being
there, and since I use these fills on internal signal layers for "planes",
in many instances, it can mean the difference on whether I get a good "fill"
and hence a good "plane" or not.

There are also some BGA routing issues where it it would be nice do "dump"
the pad "early" (so to speak) so that you can get as much other stuf fin
there as you can, and still really see what tou are doinf as well as have
the coverage of DRC.

JaMi


----- Original Message -----
From: "Michael Reagan (EDSI)" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, September 17, 2002 10:15 AM
Subject: [PEDA] Inner pad feature


> One feature I would like to see in "future" releases or service packs is
> removal of inner pads before processing gerber data.  In other terms inner
> pads would not be added to a via until a connection is made to that via.
> The reason for this is for high density connectors where I am trying to
> route between pad, I often get violations, when in fact the real gerber
data
> will have no clearance  violations after gerbers are processed with
removed
> inner pads.   This would allow proper routing in high density connectors.
> The padstack for a via would automatically represent the a via the way it
> really looks to the fabricator not to the designer.
>
> An no ,I dont want to go the way Accel did with their complicated
padstacks
> because then I have to spend time creating a complex stack library with
> silly names.  Editing vias in either PADS or Accel is time consuming,   I
> like being able to double click and everything about that object appears.
>
>
> Anybody is welcome to add to this.
>
> Mike Reagan
> EDSI
> Frederick MD

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