Abd,

Please see below,

JaMi

----- Original Message -----
From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, September 17, 2002 2:49 PM
Subject: Re: [PEDA] Inner pad feature


> At 10:49 AM 9/17/2002 -0700, Mark Koitmaa wrote:
> >Maybe your fab house can do better, but the ones I've used need at least
> >5.5 mils around a via hole to prevent break out of the hole wall. This is
> >what we use as minimum annular ring. For a decent fab yield we need at
> >least 3 mils air gap to the nearest trace. Removing the unused via pad
> >during layout doesn't buy us any extra routing room so I don't see any
> >advantage in removing the unused via pad.
>
> It is quite clear that removing unused internal pads improves yield, the
> only question is *how much* it improves yield.
>
> But it does not make the gained space safe for routing, because we can
> assume that, if routing density is an issue, via pads have been already
> been reduced in size to the minimum annular ring necessary to avoid
> breakout, as Mr. Koitmaa notes. And thus it is possible for the hole wall
> outer edge to be at the same position as the pad would have been.
>

The "extra space is extremely valuable for routing, and especially in the
case of a "via farm" undereath a large BGA, and , and since the typical pad
is usually enough oversized to account not only for "breakout" but also for
"misalignment", that means that there certainly would be room for one more
4 - 5 mil gap and one more 4 - 5 mil trace between each pair of "vias"
(holes) that do not have a connection, and hence a pad, on that layer.

> Nevertheless, this only takes place at extreme drill wander in just the
> wrong direction, and it is possible that a few mils of space could be
> gained for routing by becoming dead-pad aware in DRC. Essentially, at some
> value for the variables, the gain in yield from dropping the dead pads
> could be balanced by the loss in yield due to extreme drill wander. One
> might gain as much as a few mils of routing space.
>

Is this the exact same "extreme drill wander" that is coing to cause the
exact same hole to short to an internal plane anyway?

"Extreme drill wander" is not allowed in the manufacture of PCBs, only
"controlled wander" within the intended design tolerances.

> To determine without experiment the exact values that one could attain
> would be difficult, I think, but the problem could be approached by a
> statistical analysis assuming that drill wander is random; the results
> might vary with the number of holes, i.e., what you might get away with if
> there are a few hundred holes might be unsupportable with a few thousand.
>

Same tolerance study you are supposed to be doing on everything else on the
board.

> In any case, DRC for dead pads is not a simple matter of dropping the pads
> and taking the holes at nominal value!!!
>

Nothing in an EDA Software Application is simple, bur dealing with this
problem is no differernt than dealing with "hole to plane" clearance.

The real question is whether or not this a reasonable request,  and a
legitimate request, and is it something that should be in DXP, or in SP7.

The answers there are Yes, Yes, Yes, and Maybe.

> (By the way, there is a similar issue with inner planes, which for many
> users actually have a few mils less clearance than might appear! -- since
> Protel uses the hole size to determine inner plane clearance. For normal
> conditions, the blowouts should be 3 mils larger diametrically to make the
> real clearances on the inner plane layers the same as on positive layers.
I
> don't think DRC is aware of this at all.)
>

All part of your tolerance study.

JaMi

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