Can't you set a negative clearance for this problem?

Work out your overlay line thickness and then set the component clearance to
-(thickness/2) This should work, though it is untested.... I tend to turn
off component clearance check too, it is annoying. And really, as long as
the copper clearances are OK then your design should be alright, as long as
you don't accidentally place any component under any other component.

Also, there are three types of clearance checking. Quick check and
multilayer check are both a bit retarded, full check is still not so great,
but seems a lot better to me.

As far as what a clearance of "0" should mean, I actually think that Protel
is corrrect, as if the outer edges of two components are just touching,
there is a clearence of "0" which is what you've specified!!


Julian


--
Julian Higginson - Design Engineer - Lake Technology.
502/51-55 Mountain St, Ultimo, NSW, 2007, Australia.
mailto:[EMAIL PROTECTED] - http://www.lake.com.au 
 

> -----Original Message-----
> From: Brad Velander [mailto:[EMAIL PROTECTED]]
> Sent: Saturday, January 18, 2003 6:49 AM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] A Question About PCB Design Rules..... Protel 99SE
> SP6 .
> 
> 
> John,
>       adding to Jami's list.
> 5) Do as I do, turn off the component placement DRC check 
> completely. It
> just doesn't work in any usable manner. Use your eyes and personal
> knowledge.
>       The component placement DRC uses any land pattern item, visible,
> invisible, regardless of layer to determine the maximum extent of the
> component. It then draws a bounding box around all these items, this
> constitutes the component boundary for the placement 
> checking. Therefore any
> designator, comment, text string, etc. gets included with the 
> actual desired
> component boundary.
>       As you have found setting "0" allows placement down to 
> touching but
> will still show a violation if items actually touch. I too 
> think that this
> is a failing of Protel/Altium, a setting of "0" should allow 
> items to touch.
> It probably should allow overlap as well but I wouldn't push 
> it that far
> because I don't see that being really useful or a common need.
> 
> Sincerely,
> Brad Velander.
> 
> Lead PCB Designer
> Norsat International Inc.
> Microwave Products
> Tel   (604) 292-9089 (direct line)
> Fax  (604) 292-9010
> email: [EMAIL PROTECTED]
> http://www.norsat.com
> 
> 
> > -----Original Message-----
> > From: John Branthoover [mailto:[EMAIL PROTECTED]]
> > Sent: Friday, January 17, 2003 9:57 AM
> > To: Protel EDA Forum
> > Subject: [PEDA] A Question About PCB Design Rules..... Protel 
> > 99SE SP6.
> <SNIP>
> > 
> >     What am I doing wrong?  Any information that you can 
> > give will be greatly
> > appreciated.  Thank you for your time and have a nice day.
> > 
> > 
> > 
> > John Branthoover            :
> > Electrical Design Engineer  :
> > Acutronic  R & D            :Phone  (412) 968-1051
> > 640 Alpha Drive             :Fax    (412) 963-0816
> > Pittsburgh PA 15238         :Email  [EMAIL PROTECTED]
> > USA                         :WEB    http://www.acutronic.com
> 

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