Frankly, I don't even understand concerns about silkscreen and pads. The
silkscreen simply will not be printed over the solder area, since the
pad-mask prevents adherence of the ink to these areas.

Admittedly, one might lose bits of a character or outline this way, but the
person responsible for laying out a board should IMO be doing a visual check
after layout anyway, and this should catch any glaring problems, ie, entire
designators sitting atop ajoining pad(s)...

Okay, I admit I can see a reason for DRC'ing ref-designators vs. pad holes,
anwyay, at least for dense designs...

aj

> -----Original Message-----
> From: Robert M. Wolfe [mailto:[EMAIL PROTECTED]]
> 
> Well I guess that is also why when you move a Ref Des on a
> part that is tied to VCC or GND it take a bit of time
> to keep analyzing VCC under DRC. Never seen a
> system do that. I can see a need to specifically drc silkscreen
> to pads etc on the board but not every time you touch a Ref'Des.
> And yes you can turn off DRC bu tit still seems to do it and
> actually whay should you have to turn it off just to touch a 
> silkscreen?
> 
> From: <[EMAIL PROTECTED]>
> 
> > Okay, call me dumb, but I am having a hard time 
> > understanding how the DRC even comes into play,
> > since the clearance constraint is, by definition,
> > a constraint on copper layers only.
> > Since the silkscreen is not a copper layer, the 
> > clearance constraint shouldn't even be invoked...
> >
> > What am I missing in this "equation"?
> >
> > > From: JaMi Smith [mailto:[EMAIL PROTECTED]]
> > >
> > > John,
> > >
> > > You are not doing anything wrong, it's just Protel.
> > > From: "John Branthoover" <[EMAIL PROTECTED]>
> > >
> > > > I have two (2) position jumpers with a rectangular
> > > silkscreen drawn around them.  I want to
> > > >  place them on my PCB such that one side of
> > > the silkscreen overlap....
> > > >
> > > > When I attempt this I get a violation as soon as the
> > > silkscreen over lap....
> > > >
> > > > What am I doing wrong?  

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