Regardless of the board size the synchroniser DOES take more time than
just generating a netlist & import to PCB in the same design. 

My designs are not physically big, but pretty dense, and made out of
many SCH sheets as we heavily re-use a lot of sheet 'blocks' for system
level re-design & block re-use. I have seen the synchroniser work well
with most, but the bigger the amount of data it has to handle, worse it

I think it would be fair to say that the time difference indicates some
more 'intensive' processing or query in data (as it looks up SCH
database & PCB database at the same time?) and this would be increased
with design size and would get to a point that it would become unusable.
The synchroniser also has other quirks (like it handling of 'unmatched'
components, or especially renamed nets on ECO's) which cause it to
choke, then eventually come back with an error.

I like the synchroniser as a tool, but frequently after some failed
ECO's using it, I still have to create a discrete netlist & load into
the pcb (without errors!) after that the synchroniser will be happier. 

The difference in behaviour of the synchroniser and the straight netlist
method, as well as the additional parameters that can be set using the
synchroniser would say to me that they are quite different tools. One
parsing a netlist AND performing additional processing tasks (does not
matter what they are really) so needing more environment resources, when
the generate netlist method is purely a report tool.

In any event I always generate a discrete netlist regardless of the
forward/back annotation method used. 

Generating a discrete netlist also gives me the choice to use OTHER
layout tools instead of Protel as sometimes Protel just cannot do the
deed efficiently enough (auto jumper insert, autoroute, large designs to
name a few).

Best Regards

John A. Ross

RSD Communications Ltd
8 BorrowMeadow Road
Springkerse Industrial Estate
Stirling, Scotland FK7 7UW

Tel     +44 [0]1786 450572 Ext 225 (Office)
Tel     +44 [0]1786 450572 Ext 248 (Lab)
Fax     +44 [0]1786 474653
GSM     +44 [0]7831 373727




> -----Original Message-----
> From: Mike Reagan [mailto:[EMAIL PROTECTED] 
> Sent: Saturday, February 22, 2003 2:07 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] A Question About Netlist Compare and 
> Partially Matched Nets. Protel 99SE SP6.
>  > back and forth, so the following is more likely to reflect 
> on Mr. Regan's
> > unfamiliarity with the synchronizer, ......
> Abdul
> I would be glad to provide you with a very large design that 
> chokes Protel and makes snails pace look like a rabbit.  
> Viewing  time for a backplane pcb
> takes upwards of 1 hour just to bring it up on a 600 Mhz machine,   Of
> course  upgraded our  pcs just handle large designs like 
> these.     A fresh
> netlist import can take 4 - 6 hours.   After using the synchronizer on
> medium designs , we gave up on that avenue about a year ago.   I m not
> shaking my doodads by  stating my boards are bigger than 
> anyone else's   but
> I do know the synchronizer,  will choke for days when we 
> attempt to use it. Simply reloading the netlist  over  a 
> current netlist  will  take an entire
> day maybe until the next morning.    We cut that time down to 
> about 4 hours
> by clearing first.      I am not exaggerating   as I would be glad to
> provide you with as many different designs as you would like 
> to attempt to load.  We even killed Spectra with two designs.
> >Further, the clear process is unnecessary.<
>   Our Clear, load, connect, run drc method has come to us 
> thru long coffee
> breaks while  waiting for Protel to catch up.   I'm not knocking the
> program, because I have never used any other program for 
> designs this large therefore, I don't know how they would 
> respond either.  I would imagine any program would be slow, 
> its alot of stuff to remember. Both the netlist load and 
> synchronizer,  will go off to Thailand before the
> pc responds to any options,   We cant tolerate that as we 
> have lost too many
> man hours waiting.  We hit Cntl ALT Del  then tried another 
> way in  until I
> found out four step recovery program   (joke)    I found 
> clear to speed
> things up, the difference  in load times dropped from  
> minutes vs hours on medium size boards with maybe 1500 components
> Connect Copper...
> Well....You are sort of right .. you may have to do a little 
> work , re-assign split planes and polygons,  when you use the 
> connect copper
> command.   The DRCs will catch it, it is the last of my four steps to
> recovery.
> The four steps work without failure, every time.  I do not 
> trust a netlist load without clearing first because as we all 
> know we don'ts know which cycle even or odd the load is on.
> Mike Reagan

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