At 11:33 PM 5/13/2004, [EMAIL PROTECTED] wrote:
In theory, A 0 gap between two entites should be regard
as connected, but it is very critical, especially in the tangent condition
(Line to circle or arc, and so on), I think regard it as open is more
reasonable.


It should actually be caught by the width rule. Yes, there is a connection. Whether on the real PCB there is a connection or not could be difficult to predict. If the board is over-etched, the connection may be lost, if it is underetched, it might remain.


But the fact is that the connection does not meet the minimum width rule for the net. And I suspect that there are some other ways that minimum width could be violated that may not be checked. I've never tried it: what if a long thin fill was used to make a connection. Is the width of the fill checked?

This report, while not surprising, does point out a DRC deficiency. One may set a rule that the minimum *track* width is 10 mils, and it is easy to assume that the minimum *connection* width will therefore be 10 mils. It's not the case. Connection width is not measured in 99SE, as far as I know. Connections on inner planes can be below 10 mils; in fact, connections can be broken on inner planes due to overlap of the clearance flashes. And connection width is not measured in the case described, and possibly in some others, I haven't checked.




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